张量分析
Configuration
Spartan-3 devices are configured by loading application specific configuration data into the internal configuration memory. Configuration is carried out using a subset of the device pins, some of which are "Dedicated" to one function only, while others, indicated by the term "Dual-Purpose", can be re-used as general-purpose User I/Os once configuration is complete.Depending on the system design, several configuration modes are supported, selectable via mode pins. The mode pins M0, M1, and M2 are Dedicated pins. The mode pin settings are shown in Table 26.The HSWAP_EN input pin defines whether the I/O pins that are not actively used during configuration have pull-up resistors
during configuration. By default, HSWAP_EN is tied High (via an internal pull-up resistor if left floating) which shuts off the pull-up resistors on the user I/O pins during configuration. When HSWAP_EN is tied Low, user I/Os have pull-ups during configuration. The Dedicated configuration pins (CCLK, DONE, PROG_B, M2, M1, M0, HSWAP_EN) and the JTAG pins (TDI, TMS, TCK, and TDO) always have a pull-up resistor to VCCAUX during configuration, regardless of the value on the HSWAP_EN pin. Similarly, the dual-purpose INIT_B pin has an internal pull-up resistor to VCCO_4 or VCCO_BOTTOM,
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管理系统depending on the package style.
奶牛
笔记本电脑Depending on the chosen configuration mode, the FPGA either generates a CCLK output, or CCLK is an input accepting an externally generated clock.A persist option is available which can be used to force the configuration pins to retain their configuration function even after device configuration is complete. If the persist option is not selected then the configuration pins with the exception of CCLK, PROG_B, and DONE can be used as user I/O in normal operation. The persist option does not apply to the boundary-scan related pins. The persist feature is valuable in applications that readback configuration data after entering the User mode.Table 27 lists the total number of bits required to configure each FPGA as well as the PROMs suitable for storing those bits. See DS123: Platform Flash In-System Programmable Configuration PROMs data sheet for more information.Table 26:Spartan-3 FPGAs Configuration Mode Pin Settings
Configuration Mode (1)M0M1M2Synchronizing Clock
Data Width
Serial DOUT (2)
Master Serial 000CCLK Output 1Y
es Slave Serial 111CCLK Input 1Y es Master Parallel 110CCLK Output 8No Slave Parallel 011CCLK Input 8No JTAG 1
1
TC K Input
1
No
Notes:
1.The voltage levels on the M0, M1, and M2 pins select the configuration mode.
2.
The daisy chain is possible only in the Serial modes when DOUT is used.
Table 27:Spartan-3 FPGA Configuration Data
Device File Sizes Xilinx Platform Flash PROM
Serial Configuration
Parallel Configuration
XC3S50439,264XCF01S XCF08P XC3S2001,047,616XCF01S XCF08P XC3S4001,699,136XCF02S XCF08P XC3S10003,223,488XCF04S XCF08P XC3S15005,214,784XCF08P XCF08P XC3S20007,673,024XCF08P XCF08P XC3S400011,316,864XCF16P XCF16P XC3S5000
13,271,936
XCF16P
XCF16P
Spartan-3 FPGA Family: Functional Description
Simultaneously Switching Output Guidelines
This section provides guidelines for the maximum allowable number of Simultaneous Switching Outputs (SSOs). These guidelines describe the maximum number of user I/O pins, of a given output signal standard, that should simultaneously switch in the same direction, while maintaining a safe level of switching noise. Meeting these guidelines for the stated test conditions ensures that the FPGA operates free from the adverse effects of ground and power bounce.
Ground or power bounce occurs when a large number of outputs simultaneously switch in the same direction. The output drive transistors all conduct current to a common voltage rail. Low-to-High transitions conduct to the V CCO rail; High-to-Low transitions conduct to the GND rail. The resulting cumulative current transient induces a voltage difference across the inductance that exists between the die pad and the power supply or ground return. The inductance is associated with bonding wires, the package lead frame, and any other signal routing inside the package. Other variables contribute to SSO noise levels, including stray inductance on the PCB as well as capacitive loading at receivers. Any SSO-induced voltage consequently affects internal switching noise margins and ultimately signal quality.
Table49 and Table50 provide the essential SSO guidelines. For each device/package combination, T able49 provides the number of equivalent V CCO/GND pairs. The equivalent number of pairs is based on characterization and will possibly not match the physical number of pairs. For each output signal standard and drive strength, Table50 recommends the maximum number of SSOs, switching in the same direction, allowed per V CCO/GND pair within an I/O bank. The T able50 guidelines are categorized by package style. Multiply the appropriate numbers from T able49 and Table50 to calculate the maximum number of SSOs allowed within an I/O bank. Exceeding these SSO guidelines may result in increased power or ground bounce, degraded signal integrity, or increased system jitter.
SSO MAX/IO Bank = Table49 x Table50
The recommended maximum SSO values assume that the FPGA is soldered on the printed circuit board and that the board uses sound design practices. The SSO values do not apply for FPGAs mounted in sockets, due to the lead inductance introduced by the socket.
The number of SSOs allowed for quad-flat packages (VQ, TQ, PQ) is lower than for ball grid array packages (FG) due to the larger lead inductance of the quad-flat packages. Ball grid array packages are recommended for applications with a large number of simultaneously switching outputs.
Table 49:Equivalent V CCO/GND Pairs per Bank
Device VQ100CP132(1)(2)TQ144(1)PQ208FT256FG320FG456FG676FG900FG1156(2) XC3S501 1.5 1.52––––––
XC3S2001– 1.523–––––
XC3S400–– 1.52335–––
XC3S1000––––3355––
XC3S1500–––––356––
XC3S2000––––––569–
XC3S4000–––––––61012
XC3S5000–––––––61012
Digital Clock Manager (DCM) Timing
For specification purposes, the DCM consists of three key components: the Delay-Locked Loop (DLL), the Digital Frequency Synthesizer (DFS), and the Phase Shifter (PS).
Aspects of DLL operation play a role in all DCM applications. All such applications inevitably use the CLKIN and the CLKFB inputs connected to either the CLK0 or the CLK2X feedback, respectively. Thus, specifications in the DLL tables (Table58 and Table59) apply to any application that only employs the DLL component. When the DFS and/or the PS components are used together with the DLL, then the specifications listed in the DFS and PS tables (Table60 through Table63) supersede any corresponding ones in the DLL tables. DLL specifications that do not change with the addition of DFS or PS functions are presented in Table58 and Table59.
Period jitter and cycle-cycle jitter are two (of many) different ways of characterizing clock jitter. Both specifications describe statistical variation from a mean value.
Period jitter is the worst-case deviation from the average clock period of all clock cycles in the collection of clock periods sampled (usually from 100,000 to more than a million samples for specification purposes). In a histogram of period jitter, the mean value is the clock period.
Cycle-cycle jitter is the worst-case difference in clock period between adjacent clock cycles in the col
lection of clock periods sampled. In a histogram of cycle-cycle jitter, the mean value is zero.
Delay-Locked Loop (DLL)
Table 58:Recommended Operating Conditions for the DLL
Symbol Description Frequency Mode/
F CLKIN Range
Speed Grade
Units -5-4
一期缝合Min Max Min Max
Input Frequency Ranges
F CLKIN CLKIN_FREQ_DLL_LF Frequency for the CLKIN input Low18(2)167(3)18(2)167(3)MHz
CLKIN_FREQ_DLL_HF High48280(3)48280(3)(4)MHz Input Pulse Requirements
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CLKIN_PULSE CLKIN pulse width as a
percentage of the CLKIN period F CLKIN≤ 100 MHz40%60%40%60%-F CLKIN> 100 MHz45%55%45%55%-
Input Clock Jitter Tolerance and Delay Path Variation(5)
CLKIN_CYC_JITT_DLL_LF Cycle-to-cycle jitter at the CLKIN
input Low–±300–±300ps
CLKIN_CYC_JITT_DLL_HF High–±150–±150ps CLKIN_PER_JITT_DLL_LF Period jitter at the CLKIN input All–±1–±1ns CLKIN_PER_JITT_DLL_HF ––
CLKFB_DELAY_VAR_EXT Allowable variation of off-chip
feedback delay from the DCM
output to the CLKFB input
All–±1–±1ns
Notes:
1.DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.
2.The DFS, when operating independently of the DLL, supports lower F CLKIN frequencies. See Table60.
3.The CLKIN_DIVIDE_BY_2 attribute can be used to increase the effective input frequency range up to F BUFG. When set to TRUE,詹姆士布朗特
CLKIN_DIVIDE_BY_2 divides the incoming clock frequency by two as it enters the DCM.
4.Industrial temperature range devices have additional requirements for continuous clocking, as specified in T able64.
5.CLKIN input jitter beyond these limits may cause the DCM to lose lock. See UG331 for more details.
