PRECHARGE Operation
Input A10 determines whether one bank or all banks are to be precharged and, in the
case where only one bank is to be precharged, inputs BA[2:0] select the bank.
When all banks are to be precharged, inputs BA[2:0] are treated as “Don’t Care.” After a
bank is precharged, it is in the idle state and must be activated prior to any READ or
WRITE commands being issued.
SELF REFRESH Operation
The SELF REFRESH operation is initiated like a REFRESH command except CKE is LOW.
The DLL is automatically disabled upon entering SELF REFRESH and is automatically
enabled and reset upon exiting SELF REFRESH.
All power supply inputs (including V REFCA and V REFDQ) must be maintained at valid lev-
els upon entry/exit and during self refresh mode operation. V REFDQ may float or not
drive V DDQ/2 while in self refresh mode under certain conditions:
•V SS < V REFDQ < V DD is maintained.
•V REFDQ is valid and stable prior to CKE going back HIGH.
•The first WRITE operation may not occur earlier than 512 clocks after V REFDQ is valid.
中国红十字会尴尬现状•All other self refresh mode exit timing requirements are met.
The DRAM must be idle with all banks in the precharge state (t RP is satisfied and no
bursts are in progress) before a self refresh entry command can be issued. ODT must
also be turned off before self refresh entry by registering the ODT ball LOW prior to the
self refresh entry command (see On-Die Termination (ODT) ( for timing requirements).
If R TT,nom and R TT(WR) are disabled in the mode registers, ODT can be a “Don’t Care.”
After the self refresh entry command is registered, CKE must be held LOW to keep the
DRAM in self refresh mode.
After the DRAM has entered self refresh mode, all external control signals, except CKE
and RESET#, are “Don’t Care.” The DRAM initiates a minimum of one REFRESH com-
mand internally within the t CKE period when it enters self refresh mode.
The requirements for entering and exiting self refresh mode depend on the state of the
clock during self refresh mode. First and foremost, the clock must be stable (meeting
t CK specifications) when self refresh mode is entered. If the clock remains stable and
the frequency is not altered while in self refresh mode, then the DRAM is allowed to exit
self refresh mode after t CKESR is satisfied (CKE is allowed to transition HIGH t CKESR
later than when CKE was registered LOW). Since the clock remains stable in self refresh
mode (no frequency change), t CKSRE and t CKSRX are not required. However, if the
现代科学技术导论clock is altered during self refresh mode (if it is turned-off or its frequency changes), then t CKSRE and t CKSRX must be satisfied. When entering self refresh mode, t CKSRE
must be satisfied prior to altering the clock's frequency. Prior to exiting self refresh
mode, t CKSRX must be satisfied prior to registering CKE HIGH.
When CKE is HIGH during self refresh exit, NOP or DES must be issued for t XS time. t XS
is required for the completion of any internal refresh already in progress and must be
satisfied before a valid command not requiring a locked DLL can be issued to the de-产出
缺口 vice. t XS is also the earliest time self refresh re-entry may occur. Before a command re-
quiring a locked DLL can be applied, a ZQCL command must be issued, t ZQOPER tim-
ing must be met, and t XSDLL must be satisfied. ODT must be off during t XSDLL.
Figure 93: Self Refresh Entry/Exit Timing
CK
CK#
Command
Address
CKE
ODT 2RESET#2
Exit self refresh mode (asynchronous)
Don’t Care
Indicates break
in time scale Notes: 1.The clock must be valid and stable, meeting t CK specifications at least t CKSRE after en-
tering self refresh mode, and at least t CKSRX prior to exiting self refresh mode, if the clock is stopped or altered between states Ta0 and Tb0. If the clock remains valid and unchanged from entry
and during self refresh mode, then t CKSRE and t CKSRX do not apply; however, t CKESR must be satisfied prior to exiting at SRX.调节板
2.ODT must be disabled and R TT off prior to entering self refresh at state T1. If both R TT,nom and R TT(WR) are disabled in the mode registers, ODT can be a “Don’t Care.”
3.Self refresh entry (SRE) is synchronous via a REFRESH command with CKE LOW.
4. A NOP or DES command is required at T2 after the SRE command is issued prior to the inputs becoming “Don’t Care.”
5.NOP or DES commands are required prior to exiting self refresh mode until state Te0.
6.t XS is required before any commands not requiring a locked DLL.
7.t XSDLL is required before any commands requiring a locked DLL.
8.The device must be in the all banks idle state prior to entering self refresh mode. For example, all banks must be precharged, t RP must be met, and no data bursts can be in progress.
9.Self refresh exit is asynchronous; however, t XS and t XSDLL timings start at the first rising clock edge where CKE HIGH satisfies t ISXR at Tc1. t CKSRX timing is also measured so that t ISXR is satisfied at Tc1.
Extended Temperature Usage
Micron’s DDR3 SDRAM support the optional extended case temperature (T C) range of
0°C to 95°C. Thus, the SRT and ASR options must be used at a minimum.
The extended temperature range DRAM must be refreshed externally at 2x (double re-
fresh) anytime the case temperature is above 85°C (and does not exceed 95°C). The ex-
ternal refresh requirement is accomplished by reducing the refresh period from 64ms to
32ms. However, self refresh mode requires either ASR or SRT to support the extended
temperature. Thus, either ASR or SRT must be enabled when T C is above 85°C or self
refresh cannot be used until T C is at or below 85°C. Table 75 summarizes the two exten-
ded temperature options and Table 76 summarizes how the two extended temperature
options relate to one another.
Table 75: Self Refresh Temperature and Auto Self Refresh Description
Table 76: Self Refresh Mode Summary
Power-Down Mode
Power-down is synchronously entered when CKE is registered LOW coincident with a
NOP or DES command. CKE is not allowed to go LOW while an MRS, MPR, ZQCAL,
READ, or WRITE operation is in progress. CKE is allowed to go LOW while any of the
other legal operations (such as ROW ACTIVATION, PRECHARGE, auto precharge, or RE-
FRESH) are in progress. However, the power-down I DD specifications are not applicable
until such operations have completed. Depending on the previous DRAM state and the
command issued prior to CKE going LOW, certain timing constraints must be satisfied
(as noted in Table 77). Timing diagrams detailing the different power-down mode entry
and exits are shown in Figure 94 (page 176) through Figure 103 (page 180).
Table 77: Command to Power-Down Entry Parameters
Note: 1.If slow-exit mode precharge power-down is enabled and entered, ODT becomes asyn-
chronous t ANPD prior to CKE going LOW and remains asynchronous until t ANPD +
t XPDLL after CKE goes HIGH.
Entering power-down disables the input and output buffers, excluding CK, CK#, ODT,
CKE, and RESET#. NOP or DES commands are required until t CPDED has been satis-
fied, at which time all specified input/output buffers are disabled. The DLL should be in
a locked state when power-down is entered for the fastest power-down exit timing. If
the DLL is not locked during power-down entry, the DLL must be reset after exiting
power-down mode for proper READ operation as well as synchronous ODT operation.
During power-down entry, if any bank remains open after all in-progress commands are
complete, the DRAM will be in active power-down mode. If all banks are closed after all
in-progress commands are complete, the DRAM will be in precharge power-down
mode. Precharge power-down mode must be programmed to exit with either a slow exit
mode or a fast exit mode. When entering precharge power-down mode, the DLL is
turned off in slow exit mode or kept on in fast exit mode.
中国
威胁论The DLL also remains on when entering active power-down. ODT has special timingconstraints when slow exit mode precharge power-down is enabled and entered. Refer
to Asynchronous ODT Mode (page 197) for detailed ODT usage requirements in slow
exit mode precharge power-down. A summary of the two power-down modes is listed in
Table 78 (page 175).
While in either power-down state, CKE is held LOW, RESET# is held HIGH, and a stable
clock signal must be maintained. ODT must be in a valid state but all other input signals
are “Don’t Care.” If RESET# goes LOW during power-down, the DRAM will switch out of
power-down mode and go into the reset state. After CKE is registered LOW, CKE must
remain LOW until t PD (MIN) has been satisfied. The maximum time allowed for power-
down duration is t PD (MAX) (9 × t REFI).
The power-down states are synchronously exited when CKE is registered HIGH (with a
陕西省公众信息网
required NOP or DES command). CKE must be maintained HIGH until t CKE has been satisfied. A valid, executable command may be applied after power-down exit latency,
t XP, and t XPDLL have been satisfied. A summary of the power-down modes is listed be-
low.
For specific CKE-intensive operations, such as repeating a power-down-exit-to-refresh-
to-power-down-entry sequence, the number of clock cycles between power-down exit
and power-down entry may not be sufficient to keep the DLL properly updated. In addi-
tion to meeting t PD when the REFRESH command is used between power-down exit
and power-down entry, two other conditions must be met. First, t XP must be satisfied
before issuing the REFRESH command. Second, t XPDLL must be satisfied before the
next power-down may be entered. An example is shown in Figure 104 (page 181).
Table 78: Power-Down Modes
