SELF REFRESH Operation
健康之路慢性胃炎The SELF REFRESH command can be used to retain data in the device, even if the rest of the system is powered down. When in self refresh mode, the device retains data with-out external clocking. The device has a built-in timer to accommodate SELF REFRESH operation. The SELF REFRESH command is defined by having CS_n, RAS_n, CAS_n,and CKE held LOW with WE_n and ACT_n HIGH at the rising edge of the clock.
Before issuing the SELF REFRESH ENTRY command, the device must be idle with all banks in the precharge state and t RP satisfied. Idle state is defined as: All banks are closed (t RP , t DAL, and so on, satisfied), no data bursts are in progress, CKE is HIGH, and all timings from previous operations are satisfied (t MRD, t MOD, t RFC, t ZQinit, t ZQoper,t ZQCS, and so on). After the SELF REFRESH ENTRY command is registered, CKE must be held LOW to keep the device in self refresh mode. The DRAM automatically disables ODT termination, regardless of the ODT pin, when it enters self refresh mode and auto-matically enables ODT upon exiting self refresh. During normal operation (DLL_on),the DLL is automatically disabled upon entering self refresh and is automatically ena-bled (including a DLL reset) upon exiting self refresh.
When the device has entered self refresh mode, all of the external control signals, except CKE and RESET_n, are “Don’t Care.” For proper SELF REFRESH operation, all power supply and reference pins (V DD , V DDQ , V SS , V SSQ , V PP , and V REFCA ) must be at valid levels.The DRAM internal V REFDQ generator circuitry may remain on or be turned off depend-ing on the MR6 bit 7 setting. If the internal V REFDQ circuit is on in self refresh, the first WRITE operation or first write-leveling activity may occur after t XS time after self re-fresh exit. If the DRAM internal V REFDQ circuitry is turned off in self refresh, it ensures that the V REFDQ generator circuitry is powered up and stable within the t XSDLL period when the DRAM exits the self refresh state. The first WRITE operation or first write-lev-eling activity may not occur earlier than t XSDLL after exiting self refresh. The device ini-tiates a minimum of one REFRESH command internally within the t CKE period once it enters self refresh mode.十二烷基硫酸钠
银联商务有限公司江苏分公司The clock is internally disabled during a SELF REFRESH operation to save power. The minimum time that the device must remain in self refresh mode is t CKESR/t CKESR_PAR. The user may change the external clock frequency or halt the external clock t CKSRE/t CKSRE_PAR after self refresh entry is registered; however, the clock must be restarted and t CKSRX must be stable before the device can exit SELF REFRESH oper-ation.
The procedure for exiting self refresh requires a sequence of events. First, the clock must be stable prior to CKE going back HIGH. Once a SELF REFRESH EXIT command (SRX,combination of CKE going HIGH and DESELECT on the command bus) is registered,the following timing delay must be satisfied:
Commands that do not require locked DLL:
•t XS = ACT, PRE, PREA, REF , SRE, and PDE.
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•t XS_FAST = ZQCL, ZQCS, and MRS commands. For an MRS command, only DRAM CL, WR/RTP register, and DLL reset in MR0; R TT(NOM) register in MR1; the CWL and R TT(WR) registers in MR2; and gear-down mode register in MR3; WRITE and READ pre-amble registers in MR4; R TT(PARK) register in MR5; t CCD_L/t DLLK and V REFDQ calibra-tion value registers in MR6 may be accessed provided the DRAM is not in per-DRAM mode. Access to other DRAM mode registers must satisfy t XS timing. WRITE com-mands (WR, WRS4, WRS8, WRA, WRAS4, and WRAS8) that require synchronous ODT and dynamic ODT controlled by the WRITE command require a locked DLL. 4Gb: x4, x8, x16 DDR4 SDRAM SELF REFRESH Operation
DQS Differential Input Cross Point Voltage
To achieve tight RxMask input requirements as well as output skew parameters with re-spect to strobe, the cross point voltage of differential input signals (DQS_t, DQS_c) must meet V IX_DQS,ratio in the table below. The differential input cross point voltage V IX_DQS (V IX_DQS_FR and V IX_DQS_RF ) is measured from the actual cross point of DQS_t, DQS_c relative to the V DQS,mid of the DQS_t and DQS_c signals.
V DQS,mid is the midpoint of the minimum levels achieved by the transitioning DQS_t and DQS_c signals, and noted by V DQS_trans . V DQS_trans is the difference between the low-est horizontal tangent above V DQS,mid of the transitioning DQS signals and the highest horizontal tangent below V DQS,mid of the transitioning DQS signals. A non-monotonic transitioning signal’s ledge is exempt or not used in determination of a horizontal tan-gent provided the said ledge occurs within ±35% of the midpoint of either V IH.DIFF .Peak voltage (DQS_t rising) or V IL.DIFF .Peak voltage (DQS_c rising), as shown in the figure be-low.
A secondary horizontal tangent resulting from a ring-back transition is also exempt in determination of a horizontal tangent. That is, a falling transition’s horizontal tangent is derived from its negative slo
pe to zero slope transition (point A in the figure below), and a ring-back’s horizontal tangent is derived from its positive slope to zero slope transi-tion (point
B in the figure below) and is not a valid horizontal tangent; a rising transi-tion’s horizontal tangent is derived from its positive slope to zero slope transition (point
C in the figure below), and a ring-back’s horizontal tangent derived from its negative slope to zero slope transition (point
D in the figure below) and is not a valid horizontal tangent.
Figure 226: V IXDQS Definition
军委扩大会议D Q S _t , D Q S _c : S i n g l e - E n d e d I n p u t V o l t a g e s DQS_t
Lowest horizontal tanget above V DQS,mid DQS,mid of the transitioning signals
V SSQ V DQS_c
Table 106: Cross Point Voltage For Differential Input Signals DQS
核酸分子杂交4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – AC and DC Differential Input Meas-urement Levels
