–The voltage levels on all balls other than V DD , V DDQ , V SS , and V SSQ must be less than or equal to V DDQ and V DD on one side and must be greater than or equal to V SSQ and V SS on the other side.
–V TT is limited to 0.76V MAX when the power ramp is complete.
–V REFCA tracks V DD /2.
•Condition B:剩女
–Apply V PP without any slope reversal before or at the same time as V DD .
–Apply V DD without any slope reversal before or at the same time as V DDQ .–Apply V DDQ without any slope reversal before or at the same time as V TT and V REFCA .
–The voltage levels on all pins other than V PP , V DD , V DDQ , V SS , and V SSQ must be less than or equal to V DDQ and V DD on one side and must be larger than or
equal to V SSQ and V SS on the other side.
2.After RESET_n is de-asserted, wait for another 500μs but no longer then 3 seconds until CKE becomes active. During this time, the device will start internal state initi-alization; this will be done independently of external clocks. A reasonable attempt was made in the design to power up with the following default MR settings: gear-down mode (MR3 A[3]): 0 = 1/2 rate; per-DRAM addressability (MR3 A[4]): 0 = dis-able; maximum power-down (MR4 A[1]): 0 = disable; CS to command/address la-tency (MR4 A[8:6]): 000 = disable; CA parity latency mode (MR5 A[2:0]): 000 = disa-ble. However, it should be assumed that at power up the MR settings are unde-fined and should be programmed as shown below.
3.Clocks (CK_t, CK_c) need to be started and stabilized for at least 10ns or 5 t CK (whichever is larger) before CKE goes active. Because CKE is a synchronous signal,the corresponding setup time to clock (t IS) must be met. Also, a DESELECT com-mand must be registered (with t IS setup time to clock) at clock edge Td. After the CKE is registered HIGH after RESET, CKE needs to be continuously registered HIGH until the initialization sequence is finished, including expiration of t DLLK and t ZQinit.
4.The device keeps its ODT in High-Z state as long as RESET_n is asserted. Further,the SDRAM keeps its ODT in High-Z state after RESET_n de-assertion until CKE is registered HIGH. The ODT in
put signal may be in an undefined state until t IS be-fore CKE is registered HIGH. When CKE is registered HIGH, the ODT input signal may be statically held either LOW or HIGH. If R TT(NOM) is to be enabled in MR1,the ODT input signal must be statically held LOW. In all cases, the ODT input sig-nal remains static until the power-up initialization sequence is finished, including the expiration of t DLLK and t ZQinit.
5.After CKE is registered HIGH, wait a minimum of RESET CKE EXIT time, t XPR, be-fore issuing the first MRS command to load mode register (t XPR = MAX (t XS, 5 ×t CK).荷电
6.Issue MRS command to load MR3 with all application settings, wait t MRD.
7.Issue MRS command to load MR6 with all application settings, wait t MRD.
8.Issue MRS command to load MR5 with all application settings, wait t MRD.
9.Issue MRS command to load MR4 with all application settings, wait t MRD.
10.Issue MRS command to load MR2 with all application settings, wait t MRD.
李振华11.Issue MRS command to load MR1 with all application settings, wait t MRD.
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12.Issue MRS command to load MR0 with all application settings, wait t MOD.
13.Issue a ZQCL command to start ZQ calibration.
14.
Wait for t DLLK and t ZQinit to complete.4Gb: x4, x8, x16 DDR4 SDRAM RESET and Initialization Procedure
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杂志bration without an explicit ZQ CALIBRATION command. The earliest possible time for a ZQ CALIBRATION command (short or long) after self refresh exit is t XS, t XS_Abort, or t XS_FAST depending on operation mode.
In systems that share the ZQ resistor between devices, the controller must not allow any overlap of t ZQoper, t ZQinit, or t ZQCS between the devices.
Figure 201: ZQ Calibration Timing
T0
T1Ta0DQ Bus
Don’t Care
Ta1Ta2Ta3Tb0Tb1Tc0Tc1Tc2Command Time Break Address A10CKE
ODT CK_t
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Notes: 1.CKE must be continuously registered HIGH during the calibration procedure.
2.During ZQ calibration, the ODT signal must be held LOW and DRAM continues to pro-vide RTT_PARK.
3.All devices connected to the DQ bus should be High-Z during the calibration procedure.4Gb: x4, x8, x16 DDR4 SDRAM ZQ CALIBRATION Commands
