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RX5808 5.8G SPI通讯协议接收说明文档

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(4) SPI Digital Timing Diagram
In SPI Mode (SPI_SE = 1), the 3-wire SPI interface is used to configure the frequency as well as internal registers. Series data sequence of 3-wire SPI is shown in following Figure. This 25-bit data stream consists of 4 address bits, 1 read/write control bit and 20 data bits. Data transfer is LSB first.
During write cycle (R/W = 1), the chip will sample the SPIDATA on the rising edge of SPICLK. Sampled data will be temporally stored in internal shift register. One the rising edge of SPILE, data in shift register will be latched into specific register according to the address.
During read cycle (R/W = 0), address and read/write control bit are sampled at rising edge of SPICLK, but the data bits are sent at the falling edge of SPICLK.
LSB
1st data
MSB
2nd data
Invalid Data
SPIDATA
A0
A1
A2
A3
R/W
D0
D1
D18
D19
SPICLK
t 1
t 2
t 3
t 6
SPILE
t 7
t
t 4  t 5
Figure 6.1 Series data sequence on SPI interface
Parameter
Min.
Typ.
Max.
Unit
t1
20
-
-
ns
t2
20
-
-
ns
t3
30
-
-
ns
t4
30
-
-
ns
t5
100
-
-
ns
t6
20
点焊机电极
-
-
ns
t7
100
-
-
ns
Note:
1.) On the rising edge of the SPICLK, one bit of data is transferred into the shift register. 2.) SPILE should be “L” when the data is transferred into the shift register.

Channel Selection Table
When pin 7 (SPI_SE) is set at low voltage, the chip works as in the easy channel selection mode and the pins 4(SPIDATA/CS0), 5(SPILE/CS1), 6(SPICLK/CS2)，48(S) and 8(BX) are used for channel selection. Channel frequencies refer to below table.
SPI_SE
Band
BX
S
CS[2:0]
000
001
010
011
100
101
110
111
5GHz
0
A
0
0
5865M
5845M
5825M
5805M
5785M
5765M
5745M
5725M
0
B
0
1
5733M
5752M
5771M
5790M
5809M
5828M
5847M
5866M
Band
0
E
1
X
5705M
5685M
5665M
5645M
5885M
5905M
5925M
5945M
1
SPI
X
X
three wire SPI control pins
SPI mode
When pin 7 (SPI_SE) is set at high (3.3V), the chip works as in the SPI mode and the pins 4(SPIDATA/CS0), 5(SPILE/CS1) and 6(SPICLK/CS2) are used for ‘SPI’ inputs for 3-wire programming
Address 0x00: Synthesizer Register A
Bits
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
－
SYN_RF_R_REG [14:0]
5G Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
SYN_RF_R_REG [14:0]:
Default
5.8GHz: 0010H
R-counter divider ratio control for RF Synthesizer.
For 5.8GHz Default: 00008H
Crystal clock (Fosc )=: 8MHz
Reference clock=crystal clock/R-counter=8MHz/8=1MHz
Address 0x01: Synthesizer Register B
Bits
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
SYN_RF_N_REG [12:0]
SYN_RF_A_REG [6:0]
5G Default
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
0
1
0
1
Default
5.8GHz: 02A05H
Synthesizer counter default setting ( 5.8Ghz band:5865MHz) For 5.8Ghz band, FLO = 2*(N*32+A)*(Fosc/R)
Example: default FRF=5865MHz, FLO=5865-479=5386MHz, Fosc=8MHz, R=8 5385/2=(N*32+A)*8Mhz/8=2*(N*32+A)*1MHz
N=84(=1010100), A5(=0101) For 5.8GHz default: 02A05H
SYN_RF_N_REG [12:0]:    N counter divider ratio control for RF Synthesizer.
SYN_RF_A_REG [6:0]:    A counter divider ratio control for RF Synthesizer.
Address 0x02: Synthesizer Register C

碳纤维复合芯导线
Bits
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
AGC_6M
AGC_6M5
CC_VCO
CP_5GLO
CP_FT
SCCTL
MOUT
PRES_FT
[2:0]
[2:0]
[1:0]
[2:0]
[2:0]
[1:0]
[2:0]
Default
1
1
0
1
1
0
1
1
0
1
1
0
0
1
0
0
0
0
1
1
Default: FFE44H
AGC_6M [2:0]
6M Audio Demodulator AGC control
AGC_6M5 [2:0]
6M5 Audio Demodulator AGC control
CC_VCO [1:0]
VCO current control
CP_5GLO [2:0]
5G VCO buffer current control
CP_FT [2:0]
Charge pump current control (from 50uA to 6mA, default=100uA)
SC_CTL:
CP current test control
MOUT [1:0]
Multi-function output select
(RF R divider output, RF prescaler output, lock in detect)
PRES_FT [2:0]
Prescaler tail current control (20 ~ 140uA).
Address 0x03: Synthesizer Register D
Bits
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
－
SYN_C3
SYN_CZ
SYN_RZ
[2:0]
[2:0]
[7:0]
Default
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
0
0
0
0
0
Default: 03980H
SYN_C3 [2:0]:
Loop filter C3 control
SYN_CZ [2:0]:
Loop filter CZ control
SYN_RZ [7:0]:
Loop filter RZ control
Address 0x04: VCO Switch-Cap Control Register
Bits
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
RFVCO_EX_CAP
VCO480_EX_CAP
VCO6M _EX_CAP
VCO6M5_EX_CAP
[4:0]
[4:0]
[4:0]
[4:0]
Default
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
1
0
Default: 7ABEFH
RFVCO_EX_CAP [4:0]:
For RF VCO adjustment
480VCO_EX_CAP [4:0]:
For IF VCOadjustment
6MVCO_EX_CAP [4:0]:
For 6M VCOadjustment
6M5VCO_EX_CAP [4:0]:
For 6M5 VCOadjustment

Address 0x05: DFC Control Register
远程定向强声扩音系统耳机绕线器羊毛纸
Bits
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
_ENRECAL
R [5:0]
_OKRF
_OKIF
_OK6M
_OK6M5
VCODFC_OVP
DFC480_OVP
AUDFC_OVP
[2:0]
[2:0]
[2:0]
Default
0
1
1
1
1
1
1
0
0
0
0
1
1
1
0
1
0
0
1
0
EN_RECAL:
R [5:0]:
DFC reference clock control, set default value to 63.
OK_RF:
RF VCO fine tune
OK_IF:
IF VCO fine tune
OK_6M:
6M VCO fine tune
OK_6M5:
6M5 VCO fine tune
VCODFC_OVP [2:0]:
RF VCO setting
DFC480_OVP [2:0]:
IF VCO setting
AUDFC_OVP [2:0]:
6M/6M5 VCO setting
Address 0x06: 6M Audio Demodulator Control Register
Bits
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
6M_ICP [5:0]
6M_C3 [2:0]
6M_CZ [2:0]
6M_RZ [7:0]
Default
1
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
1
0
0
0
Default: 82408H
6M_ICP [5:0]:
6M Charge-Pump current control
6M_C3 [2:0]:
6M Loop Filter Adjusting
6M_CZ [2:0]:
6M Loop Filter Adjusting
6M_RZ [7:0]:
6M Loop Filter Adjusting
Address 0x07: 6M5 Audio Demodulator Control Register
Bits
19
18
17
16
15
14
13
12
11
10
9
黄军导航8
7
6
5
4
3
2
1
0
Name
6M5_ICP [5:0]
6M5_C3 [2:0]
6M5_CZ [2:0]
6M5_RZ [7:0]
Default
1
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
1
0
0
0
Default: 82408H
6M5_ICP [5:0]:
6M5 Charge-Pump current control
6M5_C3 [2:0]:
6M5 Loop Filter Adjusting
6M5_CZ [2:0]:
6M5 Loop Filter Adjusting
6M5_RZ [7:0]:
6M5 Loop Filter Adjusting

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