a
DSP Microcomputer Information furnished by Analog Devices is believed to be accurate and reli-able. However, no responsibility is assumed by Analog Devices for its use,nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.Tel:781/329-4700 Fax:781/326-8703 © Analog Devices, Inc., 2001
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ICE-Port is a trademark of Analog Devices, Inc.
ADSP-218xN Series
PERFORMANCE FEATURES
12.5 ns Instruction Cycle Time @1.8 V (Internal), 80 MIPS Sustained Performance
Single-Cycle Instruction Execution Single-Cycle Context Switch
桩基泥浆比重3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions Power-Down Mode Featuring Low CMOS Standby Power Dissipation with 200CLKIN Cycle Recovery from Power-Down Condition
Low Power Dissipation in Idle Mode
INTEGRATION FEATURES
ADSP-2100 Family Code Compatible (Easy to Use Algebraic Syntax), with Instruction Set Extensions Up to 256K Bytes of On-Chip RAM, Configured as Up to 48K Words Program Memory RAM Up to 56K Words Data Memory RAM
Dual-Purpose Program Memory for Both Instruction and Data Storage
Independent ALU, Multiplier/Accumulator, and Barrel Shifter Computational Units
T wo Independent Data Address Generators
Powerful Program Sequencer Provides Zero Overhead Looping Conditional Instruction Execution
Programmable 16-Bit Interval Timer with Prescaler 100-Lead LQFP and 144-Ball Mini-BGA
SYSTEM INTERFACE FEATURES
Flexible I/O Allows 1.8 V , 2.5V or 3.3V Operation All Inputs T olerate up to 3.6V Regardless of Mode 16-Bit Internal DMA Port for High-Speed Access to On-Chip Memory (Mode Selectable)
4M-Byte Memory Interface for Storage of Data T ables and Program Overlays (Mode Selectable)
8-Bit DMA to Byte Memory for T ransparent Program and Data Memory T ransfers (Mode Selectable)
Programmable Memory Strobe and Separate I/O Memory Space Permits “Glueless” System Design Programmable Wait State Generation
T wo Double-Buffered Serial Ports with Companding Hardware and Automatic Data Buffering
Automatic Booting of On-Chip Program Memory from Byte-Wide External Memory, e.g., EPROM, or through Internal DMA Port Six External Interrupts
13 Programmable Flag Pins Provide Flexible System Signaling
摄影箱UART Emulation through Software SPORT Reconfiguration
ICE-Port™ Emulator Interface Supports Debugging in Final Systems
FUNCTIONAL BLOCK DIAGRAM
ADSP-218xN Series
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VisualDSP++ and EZ-KIT Lite are trademarks of Analog Devices, Inc.
GENERAL DESCRIPTION
The ADSP-218xN series consists of six single chip micro-computers optimized for digital signal processing applica-tions. The high-level block diagram for the ADSP-218xN series members appears on the previous page. All series members are pin-compatible and are differentiated solely by the amount of on-chip SRAM. This feature, combined with ADSP-21xx code compatibility, provides a great deal of flexibility in the design decision. Specific family members are shown in Table 1.
ADSP-218xN series members combine the ADSP-2100 family base architecture (three computational units, data address generators, and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capa-bilities, and on-chip program and data memory.
ADSP-218xN series members integrate up to 256K bytes of on-chip memory configured as up to 48K words (24-bit) of program RAM, and up to 56K words (16-bit) of data RAM. Power-down circuitry is also provided to meet the low power needs of battery-operated portable equipment. The ADSP-218xN is available in a 100-lead LQFP package and 144-Ball Mini-BGA.
Fabricated in a high-speed, low-power, 0.18µm CMOS process, ADSP-218xN series members operate with a 12.5ns instruction cycle time. Every instruction can execute in a single processor cycle.
The ADSP-218xN’s flexible architecture and comprehen-sive instruction set allow the processor to perform multiple operations in parallel. In one processor cycle, ADSP-218xN series members can:
•Generate the next program address •Fetch the next instruction •Perform one or two data moves
•Update one or two data address pointers •Perform a computational operation
This takes place while the processor continues to:•Receive and transmit data through the two serial ports •Receive and/or transmit data through the internal DMA port
•Receive and/or transmit data through the byte DMA port •Decrement
timer
DEVELOPMENT SYSTEM
Analog Devices’ wide range of software and hardware development tools supports the ADSP-218xN series. The DSP tools include an integrated development environment, an evaluation kit, and a serial port emulator.
VisualDSP++™ is an integrated development environment, allowing for fast and easy development, debug, and deploy-ment. The VisualDSP++ project management environment lets programmers develop and debug an application. This environment includes an easy-to-use assembler that is based on an algebraic syntax; an archiver (librarian/library build-er); a linker; a PROM-splitter utility; a cycle-accurate, instruction-level simulator; a C compiler; and a C run-time library that
includes DSP and mathematical functions.
Debugging both C and assembly programs with the VisualDSP++ debugger, programmers can:
•View mixed C and assembly code (interleaved source and object information)•Insert break points
•Set conditional breakpoints on registers, memory, and
座便轮椅
stacks
•Trace instruction execution •Fill and dump memory •Source level debugging
The VisualDSP++ IDE lets programmers define and
manage DSP software development. The dialog boxes and property pages let programmers configure and manage all of the ADSP-218xN development tools, including the syntax highlighting in the VisualDSP++ editor. This capa-bility controls how the development tools process inputs and generate outputs.
The ADSP-2189M EZ-KIT Lite™ provides developers with a cost-effective method for initial evaluation of the powerful ADSP-218xN DSP family architecture. The ADSP-2189M EZ-KIT Lite includes a stand-alone ADSP-2189M DSP board supported by an evaluation suite of VisualDSP++. With this EZ-KIT Lite, users can learn about DSP hardware and software development and evalu-ate potential applications of the ADSP-218xN series. The ADSP-2189M EZ-KIT Lite provides an evaluation suite of the VisualDSP++ development environment with the C compiler, assembler, and linker. The size of the DSP erxecutable that can be built using the EZ-KIT Lite tools is limited to 8K words.T able 1. ADSP-218xN DSP Microcomputer Family
Device
Program Memory (K Words)
Data Memory (K Words)
六维网ADSP-2184N 44ADSP-2185N 1616ADSP-2186N 88ADSP-2187N 3232ADSP-2188N 4856ADSP-2189N 3248
ADSP-218xN Series
The EZ-KIT Lite includes the following features:
•75 MHz ADSP-2189M
•Full 16-Bit Stereo Audio I/O with AD73322 Codec •RS-232 Interface
•EZ-ICE Connector for Emulator Control
•DSP Demonstration Programs
•Evaluation Suite of VisualDSP++
The ADSP-218x EZ-ICE®Emulator provides an easier and more cost-effective method for engineers to develop and optimize DSP systems, shortening product development cycles for faster time-to-market. ADSP-218xN series members integrate on-chip emulation support with a 14-pin ICE-Port interface. This interface provides a simpler target board connection that requires fewer mechanical clearance considerations than other ADSP-2100 Family EZ-ICEs. ADSP-218xN series members need not be removed from the target system when using the EZ-ICE, nor are any adapt-ers needed. Due to the small footprint of the EZ-ICE con-nector, emulation can be supported in final board designs.The EZ-ICE performs a full range of functions, including:
•In-target operation
•Up to 20 breakpoints
•Single-step or full-speed operation
•Registers and memory values can be examined
and altered
•PC upload and download functions
•Instruction-level emulation of program booting
and execution
•Complete assembly and disassembly of instructions
• C source-level debugging
Additional Information
This data sheet provides a general overview of ADSP-
218xN series functionality. For additional information on the architecture and instruction set of the processor, refer to the ADSP-218x DSP Hardware Reference and the ADSP-218x DSP Instruction Set Reference.
ARCHITECTURE OVERVIEW
The ADSP-218xN series instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. Every instruction can be exe-cuted in a single processo
r cycle. The ADSP-218xN assem-bly language uses an algebraic syntax for ease of coding and readability. A comprehensive set of development tools sup-ports program development.
The functional block diagram is an overall block diagram of the ADSP-218xN series. The processor contains three in-dependent computational units: the ALU, the multiplier/ accumulator (MAC), and the shifter. The computational units process 16-bit data directly and have provisions to support multiprecision computations. The ALU performs a standard set of arithmetic and logic operations; division primitives are also supported. The MAC performs single-cycle multiply, multiply/add, and multiply/subtract opera-tions with 40bits of accumulation. The shifter performs logical and arithmetic shifts, normalization, denormaliza-tion, and derive exponent operations.
The shifter can be used to efficiently implement numeric format control, including multiword and block floating-point representations.
The internal result (R) bus connects the computational units so that the output of any unit may be the input of any unit on the next cycle.
A powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these computational units. The sequencer supports condi-tional jumps, subroutine cal
ls, and returns in a single cycle. With internal loop counters and loop stacks, ADSP-218xN series members execute looped code with zero overhead; no explicit jump instructions are required to maintain loops. Two data address generators (DAGs) provide addresses for simultaneous dual operand fetches (from data memory and program memory). Each DAG maintains and updates four address pointers. Whenever the pointer is used to access data (indirect addressing), it is post-modified by the value of one of four possible modify registers. A length value may be associated with each pointer to implement automatic modulo addressing for circular buffers.
Five internal buses provide efficient data transfer:•Program Memory Address (PMA) Bus
•Program Memory Data (PMD) Bus
•Data Memory Address (DMA) Bus
•Data Memory Data (DMD) Bus
•Result (R) Bus
The two address buses (PMA and DMA) share a single external address bus, allowing memory to be expanded off-chip, and the two data buses (PMD and DMD) share a single external data bus. Byte
memory space and I/O memory space also share the external buses.
Program memory can store both instructions and data, per-mitting ADSP-218xN series members to fetch two oper-ands in a single cycle, one from program memory and one from data memory. ADSP-218xN series members can fetch an operand from program memory and the next instruction in the same cycle.
In lieu of the address and data bus for external memory connection, ADSP-218xN series members may be config-ured for 16-bit Internal DMA port (IDMA port) connec-tion to external systems. The IDMA port is made up of 16
EZ-ICE is a registered trademark of Analog Devices, Inc.
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ADSP-218xN Series
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data/address pins and five control pins. The IDMA port provides transparent, direct access to the DSP’s on-chip program and data RAM.
An interface to low-cost byte-wide memory is provided by the Byte DMA port (BDMA port). The BDMA port is bidirectional and can directly address up to four megabytes of external RAM or ROM for off-chip storage of program overlays or data tables.
The byte memory and I/O memory space interface supports slow memories and I/O memory-mapped peripherals with programmable wait state generation. External devices can gain control of external buses with bus request/grant signals (BR, BGH, and BG). One execution mode (Go Mode) allows the ADSP-218xN to continue running from on-chip memory. Normal execution mode requires the processor to halt while buses are granted.
ADSP-218xN series members can respond to eleven inter-rupts. There can be up to six external interrupts (one edge-sensitive, two level-sensitive, and three configurable) and seven internal interrupts generated by the timer, the serial ports (SPORT), the Byte DMA port, and the power-down circuitry. There is also a master RESET signal. The two serial ports provide a complete synchronous serial interface with optional companding in hardware and a wide variety of framed or frameless data transmit and receive modes of operation.
Each port can generate an internal programmable serial clock or accept an external serial clock.
ADSP-218xN series members provide up to 13 general-purpose flag pins. The data input and output pins on SPORT1 can be alternatively configured as an input flag and an output flag. In addition, eight flags are programma-ble as inputs or outputs, and three flags are always outputs.A programmable interval timer generates periodic inter-rupts. A 16-bit count register (TCOUNT) decrements every n processor cycle, where n is a scaling value stored in an 8-bit register (TSCALE). When the value of the count register reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (TPERIOD).
Serial Ports
ADSP-218xN series members incorporate two complete synchronous serial ports (SPORT0 and SPORT1) for serial communications and multiprocessor communication.Following is a brief list of the capabilities of the ADSP-218xN SPORTs. For additional information on Serial Ports, refer to the ADSP-218x DSP Hardware Reference .•SPORTs are bidirectional and have a separate, double-buffered transmit and receive section.
•SPORTs can use an external serial clock or generate their own serial clock internally.
•SPORTs have independent framing for the receive and transmit sections. Sections run in a frameles
s mode or with frame synchronization signals internally or externally generated. Frame sync signals are active high or inverted, with either of two pulsewidths and timings.
•SPORTs support serial data word lengths from 3 to 16bits and provide optional A-law and µ-law compand-ing, according to CCITT recommendation G.711.•SPORT receive and transmit sections can generate unique interrupts on completing a data word transfer.•SPORTs can receive and transmit an entire circular buffer of data with only one overhead cycle per data word. An interrupt is generated after a data buffer transfer.•SPORT0 has a multichannel interface to selectively receive and transmit a 24 or 32word, time-division mul-tiplexed, serial bitstream.
•SPORT1 can be configured to have two external inter-rupts (IRQ0 and IRQ1) and the FI and FO signals. The internally generated serial clock may still be used in this configuration.
PIN DESCRIPTIONS
ADSP-218xN series members are available in a 100-lead LQFP package and a 144-Ball Mini-BGA package. In order to maintain maximum functionality and reduce package size and pin count, some serial port, programmable flag, inter-rupt and external bus pins have dual, multiplexed function-ality. The external bus pins are configured during RESET only, while serial port pins are software configur
able during program execution. Flag and interrupt functionality is retained concurrently on multiplexed pins. In cases where pin functionality is reconfigurable, the default state is shown in plain text in Table 2, while alternate functionality is shown in italics .
ADSP-218xN Series T able 2. Common-Mode Pins
Pin Name# of Pins I/O Function
RESET 1I Processor Reset Input
BR1I Bus Request Input
BG1O Bus Grant Output
BGH1O Bus Grant Hung Output
DMS1O Data Memory Select Output
PMS1O Program Memory Select Output
IOMS1O Memory Select Output
BMS1O Byte Memory Select Output
CMS1O Combined Memory Select Output
RD1O Memory Read Enable Output
WR1O Memory Write Enable Output
IRQ21I Edge- or Level-Sensitive Interrupt Request1
PF7I/O Programmable I/O pin
IRQL11I Level-Sensitive Interrupt Requests1
PF6I/O Programmable I/O Pin
IRQL01I Level-Sensitive Interrupt Requests1
PF5I/O Programmable I/O Pin
IRQE1I Edge-Sensitive Interrupt Requests1
PF4I/O Programmable I/O Pin
Mode D1I Mode Select Input—Checked Only During RESET
PF3I/O Programmable I/O Pin During Normal Operation
Mode C1I Mode Select Input—Checked Only During RESET
PF2I/O Programmable I/O Pin During Normal Operation
Mode B1I Mode Select Input—Checked Only During RESET
PF1I/O Programmable I/O Pin During Normal Operation
Mode A1I Mode Select Input—Checked Only During RESET
PF0I/O Programmable I/O Pin During Normal Operation
CLKIN1I Clock Input
XTAL1O Quartz Crystal Output
CLKOUT1O Processor Clock Output
频偏SPORT05I/O Serial Port I/O Pins
SPORT15I/O Serial Port I/O Pins
IRQ1–0, FI, FO Edge- or Level-Sensitive Interrupts, FI, FO2
PWD1I Power-Down Control Input
PWDACK1O Power-Down Acknowledge Control Output
FL0, FL1, FL23O Output Flags
V
DDINT 2I Internal V
DD
(1.8 V) Power (LQFP)
V
DDEXT 4I External V
DD
(1.8 V, 2.5 V, or 3.3 V) Power (LQFP)
GND10I Ground (LQFP)
V
DDINT 4I Internal V
DD
(1.8 V) Power (Mini-BGA)
V
DDEXT 7I External V
DD
(1.8 V, 2.5 V, or 3.3 V) Power (Mini-
BGA)
GND20I Ground (Mini-BGA)
EZ-Port9I/O For Emulation Use
1Interrupt/Flag pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, the DSP will
vector to the appropriate interrupt vector address when the pin is asserted, either by external devices or set as a programmable
flag.
2SPORT configuration determined by the DSP System Control Register. Software configurable.
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ADSP-218xN Series
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Memory Interface Pins
ADSP-218xN series members can be used in one of two modes: Full Memory Mode, which allows BDMA operation with full external overlay memory and I/O capability, or Host Mode, which allows IDMA operation with limited external addressing capabilities.
The operating mode is determined by the state of the Mode C pin during RESET and cannot be changed while the processor is running. Table 3 and Table 4 list the active
signals at specific pins of the DSP during either of the two operating modes (Full Memory or Host). A signal in one table shares a pin with a signal from the other table, with the active signal determined by the mode that is set. For the shared pins and their alternate signals (e.g., A4/IAD3), refer to the package pinouts in Table 27 on page 40 and Table 28 on page 42.
T erminating Unused Pins
Table 5 shows the recommendations for terminating unused pins.
T able 3. Full Memory Mode Pins (Mode C = 0)Pin Name
# of Pins
I/O
Function
A13–014O Address Output Pins for Program, Data, Byte, and I/O Spaces
D23–024I/O
Data I/O Pins for Program, Data, Byte, and I/O Spaces (8 MSBs are also used as Byte Memory Addresses.)T able 4. Host Mode Pins (Mode C = 1) Pin Name
# of Pins
I/O
Function
IAD15–016I/O IDMA Port Address/Data Bus
A01O Address Pin for External I/O, Program, Data, or Byte Access 1D23–816I/O Data I/O Pins for Program, Data, Byte, and I/O Spaces IWR 1I IDMA Write Enable IRD 1I IDMA Read Enable
IAL 1I IDMA Address Latch Pin IS 1I IDMA
Select
IACK 1O IDMA Port Acknowledge Configurable in Mode D; Open Drain
栅栏技术1In Host Mode, external peripheral addresses can be decoded using the A0, CMS, PMS, DMS, and IOMS signals. T able 5. Unused Pin T erminations
Pin Name
1
I/O 3-State (Z)2
Reset State
Hi-Z 3 Caused By
Unused Configuration
XTAL O O Float CLKOUT O O Float 4A13–1 or O (Z)Hi-Z BR, EBR Float IAD12–0I/O (Z)Hi-Z IS
Float A0O (Z)Hi-Z BR, EBR Float D23–8I/O (Z)Hi-Z BR, EBR Float D7 or I/O (Z)Hi-Z BR, EBR Float
IWR I
I High (Inactive)D6 or I/O (Z)Hi-Z BR, EBR Float
IRD I
I BR, EBR
High (Inactive)D5 or I/O (Z)Hi-Z Float
IAL I
I Low (Inactive)D4 or I/O (Z)Hi-Z BR, EBR
Float
IS I I
High (Inactive)
